The present invention relates to the generation of an integrated circuit, and more specifically, to model-based refinement of the placement process in integrated circuit generation.
The generation of an integrated circuit (i.e., chip) involves a number of phases including the logic design, physical synthesis, routing, and manufacturing phases. Each of the phases can include multiple processes that can be performed iteratively. The logic design can provide a register transfer level (RTL) description. The physical synthesis phase includes identifying and placing components, such as gate logic, to implement the logic design. After optimizing timing and clocks, a netlist can be produced to indicate the interconnections among components. In the routing phase, the placement of wires that connect gates and other components in the netlist is defined, and in the manufacturing phase, the finalized design is provided for physical implementation of the chip. The placement process within the physical synthesis phase ultimately determines the wiring and wire lengths that are needed in the routing phase. The placement of components that minimizes wire lengths and wiring congestion is desirable.